This invention relates to the structural details of, and processes for forming, high density layered electronic assemblies of the type which contain a stack of integrated circuit chips with conductors on one face of the stack that electrically interconnect the chips.
In the prior art, layered electronic assemblies of the above type are described in U.S. Pat. Nos. 4,704,319 to Ballinger et al, and 4,706,166 to Go. According to the teachings of Ballinger et al, such layered electronic assemblies are formed by "a rather elaborate method" which "uses three separate fixtures", --column 4, lines 5-8. The first fixture is used to "dry stack" the chips which involves selecting and stacking the chips, without any epoxy between them, based on the chip thicknesses and microscopic inspection of their circuitry; the second fixture is used to "wet stack" the chips which involves spreading uncured epoxy over the chips that are selected for the dry stack; and the third fixture is used to align the chips and hold them in alignment while the epoxy is cured. See column 6, lines 14-32; column 6, line 54 -column 7 line 5; column 7, lines 65-67 and column 9, lines 7-31.
A major drawback, however, with the Ballinger et al process is that the percentage of chips which are suitable for use in the stack is very low. Column 6, lines 14- 21 states that the percentage of chips which are suitable for stacking "may run as low as 5% of the chips originally cut from the wafers". This means that up to 95% of the chips in the wafer, which are electrically functional, are unsuitable for use in the stack.
Such a poor yield is due to the fact that in the Ballinger et al process, the chips which are used must be handpicked based on their thickness and the distance which their input/output leads (I/O leads) are located from the edge of the chip. If the thickness of the chips is ignored, then the distance of the I/O leads between chips in the stack will randomly vary; and if the distance of the I/O leads from the chip's edge of the chips is ignored, then the alignment of the I/O leads in the stack will randomly vary. In turn, these variations in the location of the I/O leads in the stack will make it difficult, if not impossible, to interconnect them with conductors on the stack's face.
How such interconnections have been made on the stack's face and how the conductors on that face have been connected to a substrate is described in U.S. Pat. No. 4,706,166 to Go. Column 4 lines 5-33 of the Go patent describes a method by which the I/O leads of the layered electronic assemblies are interconnected with patterned metal lines by processing each assembly separately. However, such processing of each stack separately presents additional serious drawbacks.
In particular, when a layer of photoresist is disposed on a single cube by spinning the cube with liquid resist on its face, the resulting layer will not be flat. Instead, the liquid resist will bead up and be thicker around the perimeter of the cube due to surface tension. Such non-uniformity in thickness limits the precision with which the resist can be patterned. This beading effect also occurs when a liquid insulating layer, such a polyimide layer, is spun on the cube's face. Further, the beading effect is cumulative and becomes larger for each spun-on layer; and that in turn, aggravates the task of interconnecting the cube's I/O leads with multiple layers of conductors.
Also, as a liquid resist or insulator is disposed on a cube's face by spin coating, the cube's face will actually spin faster than the liquid. This is because the liquid slips on the spinning face. Such slippage presents another uniformity problem since the liquid will slip off of the cube's face near its corners. Also, the liquid which slips off one corner of the cube will splatter into the next corner of the cube.
Processing each cube separately also subjects the cube to physical damage. When a cube is processed, it must somehow be handled, or moved, into and out of various processing equipment such as a sputtering machine or a photoresist spinning machine. During this handling, an I/O lead can become open-circuited by being scratched; or an insulating layer can become cracked by exerting too much pressure on it.
Go's processing of each cube separately also is very time-consuming and expensive. This becomes apparent when his method is compared to a method that is disclosed herein which reduces Go's processing time and cost by several hundred percent. Further, the method disclosed herein avoids the above beading problem and the above physical damage problem.
Accordingly, a primary object of the present invention is to address the above-described problems and overcome them.